1. Field of the Invention
The present invention relates to a power supply, and more particularly, to a current control apparatus and method employed in a power supply for limiting a maximum current.
2. Description of the Prior Art
The technology of pulse width modulation has been widely applied to a variety of switching power supplies for controlling or regulating output power. In order to avoid permanent damage occurring to a power supply, the power supply is normally embedded with protection circuits such as an over-voltage protection circuit, an over-current protection circuit, and so forth. In general, the power supply is also installed with a protection mechanism for limiting output power regarding overloading or output shorting situations.
Please refer to FIG. 1, which is a schematic diagram showing a prior-art pulse width modulation (PWM) power supply 100. Controller 106 functions to generate a PWM signal for controlling on/off states of a power switch 102. When power switch 102 is turned on, a power voltage VIN will charge the primary winding of transformer 104 making the current increase gradually flowing through the primary winding. When power switch 102 is turned off, the energy stored in transformer 104 can be released for charging an output capacitor via the secondary winding. Resistor RCS is connected with power switch 102 in series, so that voltage drop VCS across resistor RCS is corresponding to the current flowing through power switch 102 and/or the primary winding. When voltage drop VCS is greater than or equal to a predetermined value such as the value of current limit signal VLIMIT, the current, flowing through power switch 102 and/or the primary winding, is then estimated to be an over current. Under such over-current situation, controller 106 will turn off power switch 102 to cease the current flowing through the primary winding. In other words, current limit signal VLIMIT can be utilized to put a limit of maximum power output to operation of the PWM power supply 100.
However, if current limit signal VLIMIT is set as a constant, the maximum output power may change in response to a variation of power voltage VIN due to an occurrence of signal propagation delay. When voltage drop VCS is greater than or equal to the value of current limit signal VLIMIT, a signal delay time tDELAY is required for the controller 106 to complete turning off the power switch 102. In the process during the signal delay time tDELAY, the current flowing through the primary winding is still increasing, and the growth amount of the current is approximately proportional to the contemporary voltage level of power voltage VIN. That is, the maximum power output is actually increased following the increase of power voltage VIN.
A solution of the aforementioned problem is provided by Yang et al. in U.S. Pat. No. 6,674,656 filed on Oct. 28, 2002, entitled “PWM controller having a saw-limiter for output power limit without sensing input voltage”, which is referred to as '656 patent hereinafter. FIG. 2 presents a schematic diagram briefing a methodological construct regarding the '656 patent. In the methodological construct provided by the '656 patent, current limit signal VLIMIT is not a constant. A saw-tooth signal generated by oscillator 204 is furnished to waveform converter 202. Waveform converter 202 then performs slope-adjusting, clamping, and level-shifting operations on the saw-tooth signal for generating current limit signal VLIMIT as shown in FIG. 2. The value of current limit signal VLIMIT is changing with time during each period. As shown in FIG. 2, during each period, the value of current limit signal VLIMIT is rising from a lowest voltage and is eventually clamped at a highest voltage. FIG. 3 illustrates the waveforms regarding current limit signal VLIMIT and two different voltage drops VCS generated in accordance with an embodiment of the '656 patent. Referring to FIG. 3, the waveform of VCS(VINHIGH) represents the waveform of voltage drop VCS corresponding to a higher power voltage VIN, and the waveform of VCS(VINLOW) represents the waveform of voltage drop VCS corresponding to a lower power voltage VIN. Based on the waveforms shown in FIG. 3, it is obvious that the slope of voltage drop VCS(VINHIGH) is higher as the corresponding power voltage VIN is higher. Accordingly, when the power voltage VIN is higher, voltage drop VCS(VINHIGH) is rising quickly so as to reach a lower voltage of current limit signal VLIMIT, and the problem of unstable maximum output power, resulting from the occurrence of signal propagation delay, can be roughly solved.